So long then to the Intel Pathfinder for RISC-V program which shone briefly but has now been discontinued by Intel. See here: https://lnkd.in/esp7d-Hs. Just a reminder that Ashling’s RiscFree https://lnkd.in/dVwFHTr IDE and Debugger continues to remain synonymous with RISC-V as one of the market leaders in the RISC-V SDK space with broad support for all 32 and 64-bit devices offering a smooth evacuation path to Pathfinder users. Why not step on board? #riscv #Pathfinder #debug
Hugh O'Keeffe’s Post
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𝗔𝘀𝗵𝗹𝗶𝗻𝗴 𝗔𝗻𝗻𝗼𝘂𝗻𝗰𝗲𝘀 𝗦𝘂𝗽𝗽𝗼𝗿𝘁 𝗳𝗼𝗿 𝗔𝗹𝘁𝗲𝗿𝗮’𝘀 𝗔𝗴𝗶𝗹𝗲𝘅™ 𝟱 𝗙𝗣𝗚𝗔 𝗙𝗮𝗺𝗶𝗹𝘆 𝗶𝗻 𝘁𝗵𝗲𝗶𝗿 𝗥𝗶𝘀𝗰𝗙𝗿𝗲𝗲™ 𝗦𝗗𝗞 𝗮𝗻𝗱 𝗧𝗼𝗼𝗹𝗰𝗵𝗮𝗶𝗻. See our press release here: https://lnkd.in/eigK9Myg #Altera #WeareAltera #AcceleratingInnovators
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Here's a quick summary of the latest Ashling April News including support for a bunch of new RISC-V powered devices, Rust language and CHERI ISA support. We've been busy! Check it out here: https://lnkd.in/eKRHHVUm
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Great opportunity to catch up on all the latest from the OpenHW Group next week. See below...
Meet OpenHW Group at embedded world Exhibition&Conference 2024 and talk about industrial quality, open source #RISCV IP with us! 📅 9-11 April, 2024 📍 Booth 4-554 & Booth 5-119 Nuremberg (Germany) Join us at our booth 4-554 or at our Pod 5-119 and discover our new IPs and innovations. We will show our industrial grade, open Source RISC-V Cores and some use cases. Chat with Mario Rodriguez and Florian Wohlrab about how to use OpenHW IP in your next SoC! Find us at the Eclipse Foundation booth 4-554 and at the RISC-V International booth 5-119. Together with WEKA Fachmedien GmbH we also host the "SESSION 8.5 SYSTEM-ON-CHIP (SOC) DESIGN" on April 11th, great talks from Zdeněk Přikryl of Codasip, Christian Herber of NXP Semiconductors and David Cerdeira of OSYX Technologies all thanks to the detailed preparation of our own Duncan Bees More details here: https://lnkd.in/g28TKtSB We look forward to seeing you in Nuremberg and sharing a glimpse into the future of our technology with you! #OpenHW #EW24 #embeddedworld #embeddedtechnology #SoC #semiconductor Axel Sikora Renate Ester John Round Rob Wullems Andrew Moore Tiffany Sparks
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Hope to see you at Embedded World and please drop by the Embecosm Booth #146 in Hall 4.
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𝐒𝐭𝐚𝐜𝐤 𝐂𝐚𝐧𝐚𝐫𝐲 The programming term "stack canary" is inspired by the historical use of canaries in coal mines, where they served as early warning signals for toxic gases. Similarly in computing, a stack canary acts as an early warning system to detect corruption, either by a security attack like a buffer overflow or by a programming error. Here is a minimal overhead, stack canary implementation which can be used on Arm or RISC-V with GNU and LLVM 'C' toolchains. Succinct and kudos to M0AGX / LB9MG!
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Codasip's recent article on CHERI’s role in enhancing memory safety captured my attention and the transition from standard pointers to CHERI’s “atomic tokens” (aka "capabilities") could help redefine secure computing practices and pave the way for more secure software execution. The article offers a good introduction to CHERI, making it accessible for those new to the concept, and delves into the specifics of its implementation within the Codasip A730 RISC-V core. A must-read for anyone interested in the future of memory safety and secure computing. You might find my earlier CHERI post helpful here: [https://lnkd.in/eK3b_Gqn] and read the full Codasip article here: [https://lnkd.in/ed3NU8g9]. #CHERI #riscv
Securing software execution with CHERI on a Codasip A730 RISC-V core
https://riscv.org
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This is a stroke of genius and a win-win-win for all: boosting India's semiconductor economy, benefiting EDA vendors and universities, and opening vast opportunities for Indian students.
The Indian government is taking significant steps to bolster the country's semiconductor ecosystem by providing over 100 colleges with advanced electronic design automation (EDA) tools from leading companies like Siemens EDA, Synopsys, and Cadence. According to an ET report, the development aims to ensure that students are well-prepared and industry-ready upon graduation, addressing the global shortage of skilled manpower in chip design. The government's Chips to Startups (C2S) initiative, which started in January 2022, plans to train 85,000 individuals over five years in very large-scale integration and embedded system design. In its first round, 103 institutions and startups, including several Indian Institutes of Technology, were selected to work on various projects. Notably, EDA tools, which are normally very expensive, are being provided at a highly subsidized rate or as donations to educational institutions, allowing students to engage in hands-on learning and potentially incubate startups. #government #semiconductor #students #college #university #innovation #indianstartupnews
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𝐀𝐬𝐡𝐥𝐢𝐧𝐠’𝐬 𝐑𝐢𝐬𝐜𝐅𝐫𝐞𝐞™ 𝐒𝐃𝐊 𝐓𝐨𝐨𝐥𝐜𝐡𝐚𝐢𝐧 𝐧𝐨𝐰 𝐚𝐯𝐚𝐢𝐥𝐚𝐛𝐥𝐞 𝐰𝐢𝐭𝐡 𝐬𝐮𝐩𝐩𝐨𝐫𝐭 𝐟𝐨𝐫 𝐌𝐈𝐏𝐒 𝐑𝐈𝐒𝐂-𝐕 𝐈𝐒𝐀 𝐜𝐨𝐦𝐩𝐚𝐭𝐢𝐛𝐥𝐞 𝐏8700 𝐚𝐧𝐝 𝐈8500 𝐂𝐏𝐔𝐬. Thanks to some great cooperation with MIPS we are delighted to announce Ashling tools availability for their RISC-V ISA based CPUS. More on MIPS here: https://mips.com/ and details on our cooperation here: https://lnkd.in/eHhsnapU. #RISCV #MIPS #RISCFREE
Home (New)
https://mips.com
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We are still #hiring! Know anyone who might be interested?
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𝐀𝐬𝐡𝐥𝐢𝐧𝐠’𝐬 𝐑𝐢𝐬𝐜𝐅𝐫𝐞𝐞™ 𝐒𝐃𝐊 𝐧𝐨𝐰 𝐬𝐮𝐩𝐩𝐨𝐫𝐭𝐬 𝐂𝐨𝐝𝐚𝐬𝐢𝐩’𝐬 𝐜𝐨𝐧𝐟𝐢𝐠𝐮𝐫𝐚𝐛𝐥𝐞 𝐑𝐈𝐒𝐂-𝐕 𝐩𝐫𝐨𝐜𝐞𝐬𝐬𝐨𝐫𝐬 Great to announce our cooperation with Codasip, one of the leading RISC-V processor technology companies with application specific, processor customisation support including the CHERI secure RISC-V ISA. More on Codasip here: https://www.codasip.com and details on our cooperation here: https://lnkd.in/gf76Y6M6. #CODASIP #CHERI #RISCV #RISCFREE
Architect your ambition with RISC-V Custom Compute
https://codasip.com
This is very suprising. Do you know what might have been the reason for their decision ?